Semifinal Task

Task 1: Design an analog neuron with input module, neuron body, output port

Neuron receives 0s and 1s randomly.
Neuron reproduces 1 if it has more than 10 (ten) 1s in 1usec
digital input frequency: 1Ghz, pulse duration 0.5ns
digital input voltage level of 1s: 1Volt
input module converts the 0.5ns of digital pulse to 0.1ns of analog pulse with 10mV peak voltage
there is a weight in between the analog input and neuron body, that weight is adjustable by external digital signal

Design multiple neuron body to have a leaky characteristic to forget the earlier inputs; decays its internal value by half for 100ns, 200ns, 400ns, 800ns, etc.
When the neuron body produces a pulse, then the neuron forgets its input history, i.e., it resets the internal status to ‘zero’ level
Gaussian white noise source should be located between neuron body and neuron input

Task 2: Design a network which consist of multiple neurons that can distinguish the stereo (dual) inputs that the network has capability to tell which input arrives faster than the other

the single input steam is series of 1s and 0s which are distributed randomly.
the dual input streams have different strength, represented by input weight
this network tells how much dual inputs are separated in time

EDA setting

           Technology: gpdk090

Evaluation: single neuron results (50 %) and neuron network results (50%)

           Performance: justify the design is functioning as required target

           Power: 1 second accumulated power consumption, single neuron, and neuron network

           Area: single neuron layout size, neuron network layout size

           Score = performance (0 ~ 10) x power (0 ~ 10) x area (0 ~ 10) = 0 ~ 1,000

           If it is not functioning, then the score points would be zero

Due date

           2022 10 10 18:00 (earlier submission will get more credit)

Hands in

           Schematic, layout of input module, neuron body module, network module

Report of results

10-minute presentation video clip

To eric.ryu@snu.ac.kr

Comments: There will be updates on the task to specify the design condition, so please keep checking the AIX web board.